1. Field of the Invention
The present invention is related to a gate array and a manufacturing method of a semiconductor integrated circuit using the gate array, and especially to a gate array including a row composed of gate electrodes each having a different etching rate and a manufacturing method of a semiconductor integrated circuit using the gate array.
2. Background of the Invention
In a conventional gate array, since gate electrodes of P-channel and N-channel transistors are of the same shape, at first glance, it is impossible to distinguish between a row in which the P-channel transistor is formed and a row in which the N-channel transistor is formed. For example, FIG. 11 shows a layout pattern of a structure of a gate array generally called a "sea-of-gate". A semiconductor chip is formed of various elements integrated on one semiconductor substrate. In the outskirts of the semiconductor chip 1 of FIG. 11, a pad 2 connected to a lead line for electrically connecting with the outside of the semiconductor chip 1, and an I/O buffer cell 3 for buffering, for example, a signal to be exchanged between the semiconductor chip 1 and the outside thereof, are arranged. At the central portion of the semiconductor chip 1, gate electrodes 4 are arranged in arrays. In rows C1 through C7 of the gate electrodes, the conductivity type of the transistors are allotted in order, for example, "PNNPPNN".
In a general logic device, a gate length is an important factor to determine transistor performance, so that measuring and managing a gate length during process is very important. For a conventional device, since gate electrodes of P-channel and N-channel MIS transistors are formed of the same material, there is no need to distinguish the channel type of the MIS transistors to measure the gate length.
However, when the gate electrode of the P-channel MIS transistor is formed of a P-type polysilicon and the gate electrode of the N-channel MIS transistor is formed of an N-type polysilicon, their etching rates become different from each other due to the difference of impurity. Thus, for a proper management, it becomes necessary to distinguish between the P-channel and N-channel MIS transistors to measure the respective gate lengths. FIG. 13 is a graph for explaining variations in gate length between lots of the semiconductor chip. In this figure, a closed circle indicates an average gate length of the N-channel MIS transistor; an open circle indicates an average gate length of the P-channel MIS transistor; and the straight line attached to those circles indicates a distribution range (for example, three times as large as a standard deviation). In the case of FIG. 13, the gate length is managed so as to fall in the range of .+-.0.05 .mu.m centered at 0.35 .mu.m. From this figure, it is understood that, under the same etching condition, the gate length of the P-channel MIS transistor is always longer than that of the N-channel MIS transistor. Thus, the proper management is only possible with the distinction between the N-channel and P-channel MIS transistors.
Then, it becomes necessary to measure the respective gate length by making a distinction between the gate electrodes of the P-channel and N-channel MIS transistors. When the whole semiconductor chip 1 is within the visual field as shown in FIG. 11, the conductivity type of the transistors in a region AR1, for example, can be quickly distinguished as an N-type by counting the number of rows. However, when a part of the region AR1 of the semiconductor chip 1 is enlarged by a scanning electron microscope, for example, as shown in FIG. 12, to measure the gate lengths of the N-channel and the P-channel MIS transistors, it becomes difficult to distinguish the channel type of the transistors in the region AR1.
In the above-described conventional gate array and manufacturing method of the semiconductor integrated circuit using the gate array, when the gate electrodes are formed of materials having different etching rates, the gate electrodes need to be separated into groups according to their materials to measure the gate length. However, there is no mark for distinguishing between the gate electrodes at the gate electrodes or in the vicinity of the gate electrodes in the conventional gate array. Thus, for an enlarged gate electrode, it is difficult to determine which group the gate electrode to be measured, for example, belongs to, and thereby the processing time for measurement is increased.